Japanese Patent Application Laid-Open Publication No. H06-169247 (Patent Document 1) discloses an example of a circuit in which a PMOS and an NMOS are connected in parallel as a switching device, which mainly aims to reduce a conducting resistance by controlling a well potential.
Japanese Patent Application Laid-Open Publication No. 2002-135099 (Patent Document 2) discloses an example of a circuit in which a PMOS and an NMOS are connected in parallel as a switching device and a gate potential and a well potential are controlled, and which mainly aims to prevent a current inflow when applying a high voltage upon turning off the power.